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代表性論文

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“General Purpose Deep Learning Accelerator Based On Bit Interleaving"，Liang Chang, Hang Lu (路航), Chenglong Li, Xin Zhao, Zhicheng Hu, Jun Zhou, Xiaowei Li，IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD, CCF A類), Early Access.

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“Mortar-FP8: Morphing the Existing FP32 Infrastructure for High Performance Deep Learning Acceleration”，Hongyan Li, Hang Lu* (路航), Xiaowei Li，IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD, CCF A類), Early Access.

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“Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture”，Yinghao Yang, Hang Lu* (路航), Xiaowei Li，IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD, CCF A類), 2023.

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“Poseidon: Practical Homomorphic Encryption Accelerator”，Yinghao Yang, Huaizhi Zhang, Shengyu Fan, Hang Lu* (路航), Mingzhe Zhang, Xiaowei Li，IEEE 29th International Symposium on High-Performance Computer Architecture (HPCA, CCF A類), 2023.

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“BitXpro: Regularity-aware Hardware Runtime Pruning for Deep Neural Networks”，Hongyan Li, Hang Lu* (路航),?Haoxuan Wang, Shengji Deng, Xiaowei Li，IEEE Transactions on Very Large Scale Integration Systems (TVLSI, CCF B類)，2023.

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”Mortar: Morphing the Bit Level Sparsity for General Purpose Deep Learning Acceleration“，Yunhung Gao, Hongyan Li, Kevin Zhang, Xueru Yu, Hang Lu* (路航)，ACM 28th Asia and South Pacific Design Automation Conference (ASPDAC, CCF C類), 2023.

“Distilling Bit-level Sparsity Parallelism for General Purpose Deep Learning Acceleration”, Hang Lu (路航), Liang Chang, Chenglong Li, Zixuan Zhu, Shengjian Lu, Yanhuan Liu, Mingzhe Zhang, IEEE/ACM 54th International Symposium on Microarchitecture (MICRO, CCF A類)，2021.

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"Streamline Ring ORAM Accesses through Spatial and Temporal Optimization”, Dingyuan Cao, Mingzhe Zhang, Hang Lu (路航), Xiaochun Ye, Dongrui Fan, Yuezhi Che, Rujia Wang, IEEE 27th International Symposium on High-Performance Computer Architecture (HPCA, CCF A類), 2021.

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“BitX: Empower Versatile Inference for Hardware Runtime Pruning”, Hongyan Li, Hang Lu* (路航), Jiawen Huang, Wenxu Wang, Mingzhe Zhang, Wei Chen, Liang Chang, Xiaowei Li, IEEE/ACM 50th International Conference on Parallel Processing (ICPP, CCF B類)，2021.

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“Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks”, Ning Lin, Xiaoming Chen, Hang Lu (路航), Xiaowei Li, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD, CCF A類), 2021.

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“Architecting Effectual Computation for Machine Learning Accelerators”, Hang Lu* (路航), Mingzhe Zhang, Yinhe Han, Qi Wang, Huawei Li, Xiaowei Li, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD, CCF A類), 2020.

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“ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-core Processors”, Hang Lu* (路航), Yisong Chang, Ning Lin, Xin Wei, Guihai Yan, Xiaowei Li, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD, CCF A類), 2019.

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“HeadStart: Enforce Optimal Inceptions in Pruning Deep Convolutional Neural Networks for Efficient Inference on GPGPUs”, Ning Lin, Hang Lu* (路航), Xin Wei, Xiaowei Li, IEEE/ACM 56th International Design Automation Conference (DAC, CCF A類), 2019.

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“When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge Devices”, Ning Lin, Hang Lu* (路航), Xing Hu, Jingliang Gao, Xiaowei Li, IEEE 37th International Conference on Computer Design (ICCD, CCF B類), 2019.

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“VNet: A Versatile Deep Neural Network Model for Efficient Semantic Segmentation”, Ning Lin, Hang Lu* (路航), Xiaowei Li, IEEE 37th International Conference on Computer Design (ICCD, CCF B類), 2019.

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“Tetris: Re-architecting Convolutional Neural Network Computation for Machine Learning Accelerators”, Hang Lu* (路航), Xin Wei, Ning Lin, Guihai Yan, Xiaowei Li, IEEE/ACM 37th International Conference on Computer-Aided Design (ICCAD, CCF B類), 2018.

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“Redeeming Chip-level Power Efficiency by Collaborative Management of the Computation and Communication”, Ning Lin, Hang Lu* (路航), Xin Wei, Xiaowei Li, ACM 24th Asia and South Pacific Design Automation Conference (ASPDAC, CCF C類), 2018.

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“PowerTrader: Enforcing Autonomous Power Management for Large-scale Many-core Processors”, Hang Lu* (路航), Guihai Yan, Yinhe Han, Xiaowei Li, IEEE Transactions on Multi-scale Computing Systems (TMSCS), 2017.

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“RISO: Enforce Non-interfered Performance with Relaxed Network-on-Chip Isolation in Manycore Cloud Processors”, Hang Lu* (路航), Binzhang Fu, Ying Wang, Yinhe Han, Guihai Yan, Xiaowei Li, IEEE Transactions on Very Large Scale Integration Systems (TVLSI, CCF B類), 2015.

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“ShuttleNoC: Boosting On-chip Communication Efficiency Through Localized Power Adaptation”, Hang Lu* (路航), Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li, IEEE 20th Asia and South Pacific Design Automation Conference (ASPDAC, CCF C類，“最佳論文獎(jiǎng)”提名), 2015.

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“RISO: Relaxed Networks-on-Chip Isolation for Cloud Processors”, Hang Lu* (路航), Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li, IEEE/ACM 50th International Design Automation Conference (DAC, CCF A類), 2013.

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發(fā)明專利

Allocating threads on a non-rectangular area on a NoC based on predicted traffic of a smallest rectangular area，國(guó)際發(fā)明專利，授權(quán)國(guó)家：美國(guó)US9965335B2

路航，付斌章，韓銀和，李曉維

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Task allocation method, task allocation apparatus, and network-on-chip，國(guó)際發(fā)明專利，授權(quán)國(guó)家：日本JP6094005B2，韓國(guó)KR101729596B1，中國(guó)CN104156267B

路航，付斌章，韓銀和，李曉維

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一種權(quán)重捏合的卷積神經(jīng)網(wǎng)絡(luò)計(jì)算方法與系統(tǒng)，中國(guó)，201811214323.5

李曉維，魏鑫，路航

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一種卷積神經(jīng)網(wǎng)絡(luò)加速器的拆分累加器，中國(guó)，201811214639.4

李曉維，魏鑫，路航

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權(quán)重捏合神經(jīng)網(wǎng)絡(luò)加速器架構(gòu)設(shè)計(jì)，中國(guó)，201811214310.8

李曉維，魏鑫，路航

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專著和譯著

《多核處理器設(shè)計(jì)優(yōu)化——低功耗、高可靠、易測(cè)試》，科學(xué)出版社，2021.

李曉維、路航、李華偉、王穎、鄢貴海 著

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《Customizable Computing，可定制計(jì)算》，機(jī)械工業(yè)出版社，2018.

鄢貴海、葉靖、王穎、路航、盧文巖、李家軍、吳靖雅 譯，Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao 著