簡 歷：
2021年11月— 今：中科院計算所，副研究員
2020年8月 — 2021年8月：克拉克森大學(xué)，助理教授
2018年9月 — 2020年7月：華盛頓大學(xué)圣路易斯分校，博士后
2014年8月 — 2018年8月：康涅狄格大學(xué)，博士生
2011年9月 — 2014年7月：中國科學(xué)院大學(xué)，蘇州納米所，碩士生主要論著：
期刊文章:
[1] Wei Yan, Fatemeh Tehranipoor, and John A Chandy.? PUF-based fuzzy authentication without error correcting codes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(9):1445–1457, 2016.
[2] Wei Yan, Ning Zhang, Laurent Njilla, and Xuan Zhang.? PCBChain: Lightweight reconfigurable blockchain primitives for secure iot applications. IEEE Transactions on Very Large Scale Integration Systems, 2020.
[3] Fatemeh Tehranipoor, Nima Karimian, Wei Yan, and John A Chandy.?? DRAM-based intrinsic physically unclonable functions for system-level security and authentication. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(3):1085–1097, 2016.
[4] Fatemeh Tehranipoor, Paul Wortman, Nima Karimian, Wei Yan, and John A Chandy.? DVFT: A lightweight solution for power-supply noise-based TRNG using dynamic voltage feedback tuning system. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(6):1084–1097,2018.
會議文章：
[1] Wei Yan, Fatemeh Tehranipoor, and John A Chandy.?? A novel way to authenticate untrusted integrated circuits.?? In2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 132–138. IEEE, 2015.
[2] Wei Yan, Chenglu Jin, Fatemeh Tehranipoor, and John A Chandy. Phase calibrated ring oscillator PUF design and implementation on FPGAs. In2017 27th International Conference on Field Programmable Logic and Applications (FPL), pages 1–8. IEEE, 2017.
[3] Wei Yan, Fatemeh Tehranipoor, Xuan Zhang, and John Chandy. "FLASH: FPGA locality-aware sensitive hash for nearest neighbor search and clustering application." In 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), pp. 249-253. IEEE, 2020.
[4] Wei Yan, Huifeng Zhu, Zhiyuan Yu, Fatemeh Tehranipoor, John Chandy, Ning Zhang, and Xuan Zhang. "Bit 2 RNG: Leveraging Bad-page Initialized Table with Bit-error Insertion for True Random Number Generation in Commodity Flash Memory." In 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 91-101. IEEE, 2020.
科研項目：
獲獎及榮譽：
1、ICCAD 2015會議最佳論文提名
2、VLSID 2017會議最佳論文
閆闈 副研究員
研究方向：
所屬部門：高通量計算機研究中心、處理器芯片重點實驗室
導(dǎo)師類別：碩導(dǎo)
聯(lián)系方式：yanwei@ict.ac.cn
個人網(wǎng)頁：